Semiconductor device having etch stopping layer and method of forming the same

专利摘要:
A semiconductor device having an etch stop layer and a method of forming the same are provided. The method includes forming a plurality of lower patterns on a semiconductor substrate. A conformal etch stop layer is formed on a semiconductor substrate having lower patterns, and a Boro-Phosphoro Silicate Glass (BPSG) layer is formed on the etch stop layer. A flow process is performed on a semiconductor substrate having a BPSG film to form a flowed BPSG film filling a gap region between lower patterns. In this case, the etch stop layer is formed of a silicon oxide film. By the etching prevention film formed of the silicon oxide film, it is possible to protect the semiconductor substrate from the phosphoric acid that may occur during the flow process and to simplify the process to improve the productivity of the semiconductor product.
公开号:KR20040063575A
申请号:KR1020030001049
申请日:2003-01-08
公开日:2004-07-14
发明作者:권혁상；석종욱
申请人:삼성전자주식회사；
IPC主号:

专利说明:

Semiconductor device having etch stop layer and method of forming the same {Semiconductor device having etch stopping layer and method of forming the same}
[4] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a semiconductor device having an etch stop layer and a method for forming the same.
[5] In accordance with the trend of high integration of semiconductor devices, the planar area of the semiconductor devices is gradually decreasing, while the vertical height is gradually increasing. Accordingly, the step difference caused by the lower patterns has emerged as an important problem. As the pattern of the semiconductor device becomes deeper, more difficulty occurs in performing a semiconductor process, that is, a photo process or an etching process. In addition, as the aspect ratio of the gap region between the lower patterns is increased, gap-filling of the insulating layers becomes more difficult. Accordingly, researches on how to gap fill gap regions between lower patterns with insulating films and planarize insulating films have been actively conducted.
[6] Meanwhile, among the insulating films, a BPSG film, which is a silicon oxide film series, is in a flow state by a flow process, which is a thermal process. Accordingly, the BPSG film can not only gap fill gap regions between lower patterns, but can also be planarized.
[7] 1 and 2 are cross-sectional views illustrating a method of manufacturing a semiconductor device having a conventional BPSG film.
[8] 1 and 2, a plurality of gate patterns 5 are formed on the semiconductor substrate 1. The gate pattern 5 includes a gate insulating film 2, a gate electrode 3, and a capping film 4 that are sequentially stacked. Spacers 6 are formed on sidewalls of the gate pattern 5, and a conformal buffer insulating film 7 and an etch stop film 8 are sequentially formed on the entire surface of the semiconductor substrate 1 having the spacers 6. . The etch stop layer 8 is formed of a silicon nitride film. The buffer insulating layer 7 serves to buffer the stress of the etch stop layer 8. That is, the buffer insulating film 7 serves to buffer the tension stress due to the difference in the thermal expansion coefficient of the etch stop film 8 and the semiconductor substrate 1 formed of a silicon nitride film.
[9] An interlayer insulating film 9 is formed on the etch stop film 8. The interlayer insulating film 9 is formed of a BPSG film. The semiconductor substrate 1 having the interlayer insulating film 9 is subjected to a flow process which is a thermal process. Accordingly, the interlayer insulating film 9 flows to fill the gap regions between the gate patterns 5. Successively patterning the flowed interlayer insulating film 9 ′, the etch stop film 8, and the buffer insulating film 7 to expose a predetermined region of the semiconductor substrate 1 positioned between the gate patterns 5. The contact hole 10 is formed. The conductive film pattern 11 filling the inside of the contact hole 10 is formed.
[10] In the above-described prior art, phosphoric acid (H ₃ PO ₄ ) may occur due to the phosphorus P in the interlayer insulating film 9 formed of the BPSG film during the flow process. The etch stop layer 8 serves to prevent the phosphoric acid from damaging the semiconductor substrate 1. However, the processes may be complicated by the etch stop layer 8 formed of silicon nitride. In other words, as the etch stop film 8 is formed of a silicon nitride film, the buffer insulating film 7 for buffering the tension stress between the etch stop film 8 and the semiconductor substrate 1 should be formed. Further, the flowed interlayer insulating film 9 ', which is a BPSG film, and the etch stop film 8, which is a silicon nitride film, are different material films. Accordingly, when forming the contact hole 10, the etching process should be performed in two steps. As a result, the productivity of the semiconductor product can be reduced by a complicated process.
[11] SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device having an etch stop layer capable of protecting a semiconductor substrate from phosphoric acid that may be generated during a flow process of a BPSG film and improving productivity, and a method of forming the same.
[1] 1 and 2 are cross-sectional views illustrating a method of manufacturing a semiconductor device having a conventional BPSG film.
[2] 3 is a cross-sectional view for describing a semiconductor device having an etch stop layer according to a preferred embodiment of the present invention.
[3] 4 to 6 are cross-sectional views for describing a method of forming a semiconductor device having an etch stop layer according to a preferred embodiment of the present invention.
[12] Provided is a semiconductor device having an etch stop layer for solving the above technical problem. The device includes a plurality of lower patterns formed on a semiconductor substrate. An etch stop film conformally formed on the entire surface of the semiconductor substrate having the lower patterns is disposed, and a planarized BPSG film fills the gap region between the lower patterns on the etch stop layer. In this case, the etch stop layer is made of a silicon oxide film.
[13] Specifically, the lower pattern may include a gate pattern composed of a gate insulating layer, a gate electrode, and a capping layer pattern sequentially stacked on a semiconductor substrate, and a spacer formed on sidewalls of the gate pattern. The etch stop film is preferably made of a medium temperature silicon oxide film.
[14] Provided is a method of forming a semiconductor device having an anti-etching film for solving the above technical problem. The method includes forming a plurality of lower patterns on a semiconductor substrate. A conformal etch stop layer is formed on the semiconductor substrate having the lower patterns, and a BPSG film is formed on the etch stop layer. A flow process is performed on the semiconductor substrate having the BPSG film to form a flowed BPSG film filling a gap region between the lower patterns. In this case, the etch stop layer is formed of a silicon oxide film.
[15] In detail, the forming of the plurality of lower patterns may include forming a plurality of gate patterns including a gate insulating layer, a gate electrode, and a capping layer pattern sequentially stacked on a semiconductor substrate. Spacers are formed on both sidewalls of the gate pattern. In this case, the gate pattern and the spacer constitute the lower pattern. The etch stop layer is preferably formed of a medium temperature silicon oxide film.
[16] After forming the flowed BPSG film, the method may further include forming a contact hole exposing a predetermined region of the semiconductor substrate located between the lower patterns by successively patterning the flowed BPSG film and the etch stop layer. have. A conductive film pattern is formed to fill the inside of the contact hole.
[17] Before forming the contact hole, the method may further include planarizing the flowed BPSG film by a chemical mechanical polishing process. Furthermore, after planarization by the chemical mechanical polishing process, a cap interlayer insulating film may be further formed on the planarized BPSG film. In this case, the contact hole is formed by successively patterning the cap interlayer insulating layer, the planarized BPSG layer, and the etch stop layer.
[18] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.
[19] 3 is a cross-sectional view for describing a semiconductor device having an etch stop layer according to a preferred embodiment of the present invention.
[20] Referring to FIG. 3, a plurality of lower patterns 115 are disposed on the semiconductor substrate 101. The lower pattern 115 may include a gate pattern 110 formed on the semiconductor substrate 101 and a spacer 114 formed on sidewalls of the gate pattern 110. The gate pattern 110 includes a gate insulating layer 105, a gate electrode 107, and a capping layer pattern 109 that are sequentially stacked on the semiconductor substrate 101. The gate insulating layer 105 may be formed of a thermal oxide layer. The gate electrode 107 may be formed of a doped polysilicon layer or a polyside layer. The polyside film is composed of a doped polysilicon film and a metal silicide film sequentially stacked. The capping layer pattern 109 and the spacer 114 may be formed of a silicon nitride layer.
[21] An etch stop layer 116 conformally formed on the lower patterns 115 and the surface of the semiconductor substrate 101 is disposed. The etch stop layer 116 is made of a silicon oxide layer. For example, it is preferable that it consists of Middle Temperature Oxide (MTO). As a result, a conventional buffer insulating film is not required.
[22] A planarized interlayer insulating film 118a ′ is disposed on the etch stop layer 116 to fill a gap region between the lower patterns 115. The planarized interlayer insulating film 118a 'is preferably made of a BPSG film. The BPSG film may be in a flattened state by using a chemical mechanical polishing (CMP) process on the upper surface of the flowed state or the flowed state. In this case, the etch stop layer 116 prevents the semiconductor substrate 101 from being damaged from phosphoric acid that may occur during the flow process of the BPSG layer.
[23] A cap interlayer insulating layer 120 is disposed on the planarized interlayer insulating layer 118a '. The cap interlayer insulating film 120 is formed of a silicon oxide film. For example, it may be made of a CVD silicon oxide film. In particular, the cap interlayer insulating film 120 may be formed of the same BPSG film as the planarized interlayer insulating film 118a '. The cap interlayer insulating layer 120 may be omitted.
[24] A conductive layer penetrating the cap interlayer insulating layer 120, the planarized interlayer insulating layer 118a ′, and the etch stop layer 116 and contacting a predetermined region of the semiconductor substrate 101 positioned between the lower patterns 115. The film pattern 124 is disposed. The conductive layer pattern 124 may have a plug shape.
[25] 4 to 6 are cross-sectional views for describing a method of forming a semiconductor device having an etch stop layer according to a preferred embodiment of the present invention.
[26] Referring to FIG. 4, an isolation region 103 is formed on the semiconductor substrate 101 to define an active region. The device isolation film 103 may be formed of a silicon oxide film, or may be formed of a trench device isolation film. A plurality of gate patterns 110 are formed across the active region. The gate pattern 110 includes a gate insulating layer 105, a gate electrode 107, and a capping layer pattern 109 that are sequentially stacked. The gate insulating layer 105 may be formed of a thermal oxide layer, and the gate electrode 107 may be formed of a doped polysilicon layer or a polyside layer. The capping layer pattern 109 may be formed of a silicon nitride layer.
[27] Impurity ions are implanted using the gate pattern 110 and the device isolation layer 103 as a mask to form an impurity diffusion layer 112 in the active regions on both sides of the gate pattern 110. Subsequently, spacers 114 are formed on sidewalls of the gate pattern 110. The spacer 114 may be formed of a silicon nitride film. The impurity diffusion layer 112 may be formed to have a lightly doped drain (LDD) structure. The gate pattern 110 and the spacer 114 constitute a lower pattern 115.
[28] A conformal etch stop layer 116 is formed on the entire surface of the semiconductor substrate 101 having the spacer 114. The etch stop layer 116 is formed of a silicon oxide layer. For example, it is preferable to form with the medium temperature silicon oxide film formed by CVD method.
[29] An interlayer insulating layer 118 is formed on the etch stop layer 116. The interlayer insulating film 118 is formed of a BPSG film.
[30] 5 and 6, a flow process, which is a thermal process, is performed on the semiconductor substrate 101 having the interlayer insulating film 118 to form a flowed interlayer insulating film 118a. Due to the flow process, the interlayer insulating film 118 is planarized by moving boron and phosphorus (B, P) elements therein. In this case, the flowed interlayer insulating layer 118a fills the gap regions between the lower patterns 115, that is, the gate patterns 110.
[31] In the above-described forming method, even when phosphoric acid is generated due to the phosphorus P in the interlayer insulating film 118 during the flow process, the semiconductor substrate 101 is protected by the etching prevention film 116. In addition, since the etch stop layer 116 is formed of a silicon oxide layer, a buffer insulating layer that buffers stress of the etch stop layer of the conventional silicon nitride layer is not required. As a result, the process can be simplified to improve the productivity of the semiconductor product.
[32] Subsequently, the planarization process using the chemical mechanical polishing (CMP) process is further performed to further planarize the flowed interlayer insulating film 118a. A cap interlayer insulating film 120 is formed on the interlayer insulating film 118a 'planarized by the CMP process. The cap interlayer insulating film 120 is formed of a silicon oxide film. For example, it can be formed from a CVD silicon oxide film. In particular, the cap interlayer insulating film 120 may be formed of the same BPSG film as the planarized interlayer insulating film 118a '. In this case, the BPSG film formed of the cap interlayer insulating film 120 may omit a flow process. This is due to the planarized interlayer insulating film 118a 'below. The planarization process using the CMP process and the process of forming the cap interlayer insulating film 120 may be omitted.
[33] A predetermined region of the impurity diffusion layer 112 positioned between the lower patterns 115 by successively patterning the cap interlayer insulating layer 120, the planarized interlayer insulating layer 118a ′, and the etch stop layer 116. A contact hole 122 is formed to expose the gap. The contact hole 122 may be self-aligned by the spacer 114 and the capping layer pattern 109. The conductive layer pattern 124 filling the inside of the contact hole 122 is formed.
[34] When the contact hole 122 is formed, all of the etching layers 120, 118a ′, and 116 are silicon oxide layers. Accordingly, the contact hole 122 may be formed by performing an etching process in one step. That is, since the etch stop layer 116 is formed of a silicon oxide layer, the process may be simplified as compared with the contact hole formed in two steps by the conventional silicon nitride layer. Thereby, productivity of a semiconductor product can be improved.
[35] As described above, according to the present invention, the etching prevention film is formed of a silicon oxide film. Accordingly, during the flow process of the BPSG film formed on the etch stop layer, the semiconductor substrate may be prevented from being damaged by phosphoric acid that may be generated, and the productivity of the semiconductor product may be improved by simplifying the process as compared with the related art.

权利要求:
Claims (11)
[1" claim-type="Currently amended] A plurality of lower patterns formed on the semiconductor substrate;
An etch stop film conformally formed on the entire surface of the semiconductor substrate having the lower patterns; And
And a planarized BPSG film disposed on the etch stop layer and filling a gap region between the lower patterns, wherein the etch stop layer is formed of a silicon oxide film.
[2" claim-type="Currently amended] The method of claim 1,
The lower pattern is,
A gate pattern composed of a gate insulating film, a gate electrode, and a capping film pattern sequentially stacked on the semiconductor substrate; And
And a spacer formed on sidewalls of the gate pattern.
[3" claim-type="Currently amended] The method of claim 1,
The etch stop layer is a semiconductor device, characterized in that consisting of a medium temperature silicon oxide film.
[4" claim-type="Currently amended] The method of claim 1,
And a conductive layer pattern penetrating the planarized BPSG layer and the etch stop layer to contact the semiconductor substrate between the lower patterns.
[5" claim-type="Currently amended] The method of claim 4, wherein
And a cap interlayer insulating film formed on the planarized BPSG film, wherein the conductive film pattern passes through the cap interlayer insulating film, the planarized BPSG film, and the etch stop layer.
[6" claim-type="Currently amended] Forming a plurality of lower patterns on the semiconductor substrate;
Forming a conformal etch stop layer on the semiconductor substrate having the lower patterns;
Forming a BPSG film on the etch stop layer; And
And forming a flowed BPSG film filling the gap region between the lower patterns by performing a flow process on the semiconductor substrate having the BPSG film, wherein the etch stop layer is formed of a silicon oxide film. Way.
[7" claim-type="Currently amended] The method of claim 6,
The forming of the plurality of lower patterns may include:
Forming a plurality of gate patterns including a gate insulating layer, a gate electrode, and a capping layer pattern sequentially stacked on the semiconductor substrate; And
And forming spacers on both sidewalls of the gate pattern, wherein the gate pattern and the spacer constitute the lower pattern.
[8" claim-type="Currently amended] The method of claim 6,
The etching prevention film is a method of forming a semiconductor device, characterized in that formed by the Middle Temperature Oxide (MTO).
[9" claim-type="Currently amended] The method of claim 6,
After the flowed BPSG film is formed,
Successively patterning the flowed BPSG layer and the etch stop layer to form a contact hole exposing a predetermined region of the semiconductor substrate located between the lower patterns; And
And forming a conductive film pattern filling the inside of the contact hole.
[10" claim-type="Currently amended] The method of claim 8,
Before forming the contact hole,
And planarizing the flowed BPSG film by a chemical mechanical polishing process.
[11" claim-type="Currently amended] The method of claim 10,
After the planarization step by the chemical mechanical polishing process,
And forming a cap interlayer dielectric layer on the planarized BPSG layer, wherein the contact hole is formed by successively patterning the cap interlayer dielectric layer, the planarized BPSG layer and the etch stop layer. Method of formation.

类似技术:

---

公开号 | 公开日 | 专利标题

---

US9337147B2|2016-05-10|Semiconductor device and a method of manufacturing the same and designing the same

---

KR101815527B1|2018-01-05|Semiconductor device and method for manufacturing the same

---

US8294236B2|2012-10-23|Semiconductor device having dual-STI and manufacturing method thereof

---

TWI517262B|2016-01-11|Semiconductor structures integrating damascene-body finfet's and planar devices on a common substrate and methods for forming such semiconductor structures

---

US7868411B2|2011-01-11|Semiconductor devices

---

US7045875B2|2006-05-16|Semiconductor device with self-aligned junction contact hole and method of fabricating the same

---

US6528368B1|2003-03-04|Method for fabricating semiconductor device, and semiconductor device, having storage node contact flugs

---

KR101471858B1|2014-12-12|Semiconductor device having bar type active pattern and method of manufacturing the same

---

TWI509736B|2015-11-21|Finfets having dielectric punch-through stoppers

---

US7071517B2|2006-07-04|Self-aligned semiconductor contact structures and methods for fabricating the same

---

KR100618861B1|2006-08-31|Semiconductor device having local recess channel transistor and method of fabricating the same

---

KR100515061B1|2005-09-14|Semiconductor devices having a fin field effect transistor and methods for forming the same

---

US6476444B1|2002-11-05|Semiconductor device and method for fabricating the same

---

KR100714900B1|2007-05-04|Semiconductor device having buried gate electrode and fabrication method thereof

---

KR100496891B1|2005-06-23|Silicon fin for finfet and method for fabricating the same

---

US6432774B2|2002-08-13|Method of fabricating memory cell with trench capacitor and vertical transistor

---

US7029989B2|2006-04-18|Semiconductor device and method of manufacturing the same

---

JP5073157B2|2012-11-14|Semiconductor device

---

JP4086926B2|2008-05-14|Semiconductor device and manufacturing method thereof

---

JP3571301B2|2004-09-29|Method for forming contact hole in semiconductor device

---

KR100545863B1|2006-01-24|Semiconductor device having a fin structure and method of manufacturing the same

---

KR100847308B1|2008-07-21|Semiconductor device and method for manufacturing the same

---

US6355529B2|2002-03-12|Method of fabricating memory cell with vertical transistor

---

KR101116360B1|2012-03-09|Semiconductor device with buried bitline and method for manufacturing the same

---

KR100598098B1|2006-07-07|Metal-Oxide-Semiconductor Having Buried Insulation Region And Methods Of Fabricating The Same

同族专利:

---

公开号 | 公开日

---

引用文献:

---

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

---

法律状态:
2003-01-08|Application filed by 삼성전자주식회사

---

2003-01-08|Priority to KR1020030001049A

---

2004-07-14|Publication of KR20040063575A

优先权:

---

申请号 | 申请日 | 专利标题

---

KR1020030001049A|KR20040063575A|2003-01-08|2003-01-08|Semiconductor device having etch stopping layer and method of forming the same|